1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and an operation method using the same.
2. Related Art
A semiconductor memory apparatus stores data and outputs the stored data.
In more detail, a general semiconductor memory apparatus stores data in response to a command from a controller or a central processing unit, and outputs the stored data.
As illustrated in FIG. 1, the general semiconductor memory apparatus includes a command input block 10, a command processing block 20, a memory block 30, a memory control block 40, a sense amplifier 50, a data comparison block 60, and a voltage control block 70 for writing.
The command input block 10 may convert an external command CMD_ext input from an exterior to an internal command CMD_int.
The command processing block 20 decodes the internal command CMD_int, and enables a read signal read_s when the internal command CMD_int is determined as a read command. When the internal command CMD_int is determined as a write command, the command processing block 20 enables the read signal read_s for a predetermined time, and enables a write signal write_s when the read signal read_s is disabled. When one of the read signal read_s and the write signal write_s is enabled, the command processing block 20 enables an operation signal operation_s.
The memory block 30 stores data. For example, the memory block 30 includes a resistive memory element R_cell having a resistance value varying according to the level of an applied voltage or the amount of an applied current. The memory control block 40 is electrically coupled to a first end of the resistive memory element R_cell, and a ground terminal VSS is electrically coupled to a second end of the resistive memory element R_cell, the first end facing the second end.
The memory control block 40 allows a predetermined amount of current to flow through the memory block 30 or applies a voltage having a specific level to the memory block 30 in response to first and second voltage supply control signals V_sup1 and V_sup2, the write signal write_s, the read signal read_s, and the operation signal operation_s. The memory control block 40 electrically couples the memory block 30 to the sense amplifier 50. For example, when the write signal write_s is enabled, the memory control block 40 supplies the memory block 30 with a predetermined voltage or a predetermined amount of current in response to the first and second voltage supply control signals V_sup1 and V_sup2. When the read signal read_s is enabled, the memory control block 40 electrically couples the sense amplifier 50 to the memory block 30.
The memory control block 40 includes a voltage supply selection unit 31, a memory voltage supply unit 32, and first to third switches 33, 34, and 35.
The voltage supply selection unit 31 provides the voltage supply unit 32 with a first voltage V_set for writing and a second voltage V_reset for writing in response to the first and second voltage supply control signals V_sup1 and V_sup2. For example, the voltage supply selection unit 31 supplies the voltage supply unit 32 with one of the first voltage V_set for writing and the second voltage V_reset for writing in response to the first and second voltage supply control signals V_sup1 and V_sup2. The voltage supply selection unit 31 does not supply the voltage supply unit 32 with both of the first voltage V_set for writing and the second voltage V_reset for writing in response to the first and second voltage supply control signals V_sup1 and V_sup2.
The voltage supply selection unit 31 includes a first voltage supply section 31-1 for writing and a second voltage supply section 31-2 for writing.
The first voltage supply section 31-1 for writing is activated in response to the first voltage supply control signal V_sup1, and the activated first voltage supply section 31-1 for writing generates the first voltage V_set for writing. The deactivated first voltage supply section 31-1 for writing does not generate the first voltage V_set for writing.
The second voltage supply section 31-2 for writing is activated in response to the second voltage supply control signal V_sup2, and the activated second voltage supply section 31-2 for writing generates the second voltage V_reset for writing. The deactivated second voltage supply section 31-2 for writing does not generate the second voltage V_reset for writing.
The voltage supply unit 32 generates a memory voltage V_wr in response to one voltage level of the first and second voltages V_set and V_reset. For example, the voltage supply unit 32 generates a memory voltage V_wr having a first voltage level when the first voltage V_set for writing is applied, and generates a memory voltage V_wr having a second voltage level when the second voltage V_reset for writing is applied.
The voltage supply unit 32 includes a transistor P1. The transistor P has a gate, which is electrically coupled to a node electrically coupled to the output terminals of the first voltage supply section 31-1 for writing and the second voltage supply section 31-2 for writing, a source that receives a driving voltage V_drv, and a drain that outputs the memory voltage V_wr.
The first switch 33 transfers the memory voltage V_wr to a common node Node_com in response to the write signal write_s. For example, when the write signal write_s is enabled, the first switch 33 transfers the memory voltage V_wr to the common node Node_com.
The second switch 34 electrically couples the sense amplifier 50 to the common node Node_com in response to the read signal read_s. For example, when the read signal read_s is enabled, the second switch 34 electrically couples the sense amplifier 50 to the common node Node_com.
The third switch 35 electrically couples the common node Node_com to the memory block 30 in response to the operation signal operation_s. For example, when the operation signal operation_s is enabled, the third switch 35 electrically couples the common node Node_com to the memory block 30. That is, when the operation signal operation_s is enabled, the third switch 35 electrically couples the common node Node_com to the resistive memory element R_cell.
When the read signal read_s is enabled and the sense amplifier 50 is electrically coupled to the memory block 30, the sense amplifier 50 determines data stored in the memory block 30 and generates storage data Data_sa. For example, when the read signal read_s is enabled, the sense amplifier 50 determines a resistance value of the memory block 30 and generates the storage data Data_sa.
The data comparison block 60 compares input data Data_in input from an exterior with the storage data Data_sa, and generates first and second control signals ctrl1 and ctrl2. For example, when the input data Data_in is substantially equal to the storage data Data_sa, the data comparison block 60 disables the first and second control signals ctrl1 and ctrl2. When the input data Data_in is different from the storage data Data_sa, the data comparison block 60 enables one of the first and second control signals ctrl1 and ctrl2. When the input data Data_in is different from the storage data Data_sa, the data comparison block 60 enables one of the first and second control signals ctrl1 and ctrl2 according to a data value of the input data Data_in.
The voltage control block 70 for writing generates the first and second voltage supply control signals V_sup1 and V_sup2 in response to the first and second control signals ctrl1 and ctrl2. For example, when the first and second control signals ctrl1 and ctrl2 are disabled, the voltage control block 70 for writing disables the first and second voltage supply control signals V_sup1 and V_sup2. When the first control signal ctrl1 of the first and second control signals ctrl1 and ctrl2 is enabled, the voltage control block 70 for writing enables the first voltage supply control signal V_sup1. When the second control signal ctrl2 of the first and second control signals ctrl1 and ctrl2 is enabled, the voltage control block 70 for writing enables the second voltage supply control signal V_sup2.
The general semiconductor memory apparatus configured as above operates as follows.
In a read operation, the external command CMD_ext is converted to the internal command CMD_int, so that the command processing block 20 enables the read signal read_s.
The memory block 30 is electrically coupled to the sense amplifier 50 through the second and third switches 34, and 35.
The sense amplifier 50 determines a data value of the memory block 30 to generate the storage data Data_sa. At this time, in the read operation, the storage data Data_sa is output to an exterior through a data output circuit (not illustrated).
In a write operation, the external command CMD_ext is converted to the internal command CMD_int and is input to the command processing block 20. The command processing block 20 enables the read signal read_s for a predetermines, disables the read signal read_s, and enables the write signal write_s after the read signal read_s is disabled.
In the write operation, when the read signal read_s is enabled, the semiconductor memory apparatus performs a preliminary read operation. Hereinafter, the preliminary read operation will be described.
When the read signal read_s is enabled, the memory block 30 is electrically coupled to the sense amplifier 50 through the second and third switches 34, and 35. The sense amplifier 50 determines the data value of the memory block 30 to generate the storage data Data_sa. An operation for generating the storage data Data_sa according to the read signal read_s that is enabled in the write operation will be referred to as the preliminary read operation. Hereinafter, an operation subsequent to the preliminary read operation will be described.
In the write operation, the data comparison block 60 compares the input data Data_in input from an exterior with the storage data Data_sa, and generates the first and second control signals ctrl1 and ctrl2. When the input data Data_in is substantially equal to the storage data Data_sa, the data comparison block 60 disables the first and second control signals ctrl1 and ctrl2. When the input data Data_in is different from the storage data Data_sa, the data comparison block 60 enables one of the first and second control signals ctrl1 and ctrl2 according to the data value of the input data Data_in. For example, when the input data Data_in is different from the storage data Data_sa and the data value of the input data Data_in is at a high level, the data comparison block 60 enables the first control signal ctrl1. When the input data Data_in is different from the storage data Data_sa and the data value of the input data Data_in is at a low level, the data comparison block 60 enables the second control signal ctrl2.
The voltage control block 70 for writing disables the first and second voltage supply control signals V_sup1 and V_sup2 when the first and second control signals ctrl1 and ctrl2 are disabled. When the first control signal ctrl1 is enabled, the voltage control block 70 for writing enables the first voltage supply control signal V_sup1. When the second control signal ctrl2, is enabled, the voltage control block 70 for writing enables the second voltage supply control signal V_sup2.
The first voltage supply section 31-1 for writing provides the first voltage V_set for writing to the memory voltage supply unit 32 when the first voltage supply control signal V_sup1 is enabled.
The second voltage supply section 31-2 for writing provides the second voltage V_reset for writing to the memory voltage supply unit 32 when the second voltage supply control signal V_sup2 is enabled.
The memory voltage supply unit 32 generates the memory voltage V_wr in correspondence with one voltage level of the first and second voltages V_set and V_reset for writing.
The memory voltage V_wr is applied to the memory block 30 through the first and third switch 33 and 35 turned on by the write signal write_s.
The memory block 30 decides a data valve according to a voltage level of the memory voltage V_wr and stores the decided data value. For example, the resistive memory element R_cell included in the memory block 30 has a resistance value varying according to the voltage level of the memory voltage V_wr.
The general semiconductor memory apparatus stores data as described above and outputs the stored data.
When the stored data is substantially equal to data input from an exterior, that is, data to be stored, the general semiconductor memory apparatus has only to maintain the stored data. However, when the stored data is different from the data to be stored, the general semiconductor memory apparatus activates one of the first and second voltage supply sections 31-1 and 31-2 for writing according to a data value of the data to be stored. A memory voltage V_wr having a voltage level corresponding to a level of a voltage output from the activated voltage supply section for writing is applied to the memory block 30, so that data is stored in the memory block 30. At this time, when the stored data is different from the data to be stored, one of the first and second voltage supply sections 31-1 and 31-2 for writing is activated according to the data value of the data to be stored. Immediately after being activated, the voltage supply section 31-1 or 31-2 for writing does not generate the voltage V_set or V_reset for writing at its own target level. That is, after the first and second voltage supply sections 31-1 and 31-2 for writing are activated and a predetermined time passes, the first and second voltage supply sections 31-1 and 31-2 for writing generate the first and second voltage V_set and V_reset for writing at their own target levels. Therefore, since the memory voltage V_wr generated according to the voltage levels of the first and second voltage V_set and V_reset for writing are also not generated at a normal voltage level, the memory block 30 storing data by the memory voltage V_wr does not normally store data. In brief, until one of the first and second voltage supply sections 31-1 and 31-2 for writing is activated and generates the first or second voltage V_set or V_reset for writing at its own target level, the memory block 30 does not store normal data. Therefore, in the write operation, until the first and second voltage supply sections 31-1 and 31-2 for writing generate the first and second voltage V_set and V_reset for writing at their own target levels, since the general semiconductor memory apparatus is not able to complete the write operation, a completion time of the write operation becomes too long.